1. Field of the Invention
This disclosure relates to a semiconductor integrated-circuit device and more particularly to a semiconductor integrated-circuit device with standard cells, each having a standard capacitor.
2. Discussion of the Related Art
In general, large-scale logic circuits have been implemented in a gate array, a cell based integrated-circuit, and others. These integrated circuits include a plurality of unit circuits which are called “cells”.
The cells are classified into a logic cell, a memory cell, and a standard cell. The logic cells each include a logic circuit which consists of at least one of NAND, NOR, AND, OR, or other types of gates. The memory cell has a predetermined configuration. That is, the memory cell may be configured or programmed in a previously desired state as flash memory. The standard cell connects the logic cells with each other or the memory cell with the logic cell. To this end, the standard cell is positioned between the logic cells or between the memory cell and the logic cell. Such cells are formed by completing a mask pattern layout.
With respect to the cells, positions of input and output terminals, a response speed, and the mask pattern layout are previously determined. These cell specifications are stored in an auxiliary memory device for an integrated-circuit design support. This auxiliary memory device for the integrated-circuit design support can enable a semiconductor integrated-circuit device with a logical function to be implemented by placing the cells on a chip and connecting the cells using wiring.
The semiconductor integrated-circuit is designed through a placement and routing process. The placement and routing process arranges a plurality of memory cells, a plurality of logic cells having a variety of logical functions, and a plurality of standard cells (called “filter cells”) on a semiconductor integrated-circuit chip through a placement stage, and thereafter forms a plurality of lines through a routing stage. In this case, the standard cell performs only a single function connecting the logic circuits which perform logical operations such as AND and OR operations. In other words, the standard cell does not include any circuit element in it.
The plurality of logic cells and the plurality of memory cells are arranged on a core area of the semiconductor integrated-circuit device. When a glitch phenomenon of power/ground is caused in the core area of the semiconductor integrated-circuit device by external and internal factors, it is difficult to compensate. Also, the semiconductor integrated-circuit device is easily affected by electromagnetic interference (EMI) generated in the logic cells and the memory cells.
In order to compensate for the power/ground glitch phenomenon and the electromagnetic interference, additional compensation circuits can be included in the semiconductor integrated-circuit device. However, the additional compensation circuits may reduce the internal area of the semiconductor integrated-circuit device.